HD6473258P10 Renesas Electronics America, HD6473258P10 Datasheet - Page 161

• Manufacturer Part Number: HD6473258P10
• Description: IC H8 MCU OTP 32K 64DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/325r

Specifications of HD6473258P10

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI, UART/USART
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Peripherals: -

8.2.2 Time Constant Registers A and B (TCORA and TCORB) – H’FFCA and H’FFCB
Bit
Initial value
Read/Write
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO0 or TMO1) is controlled by these compare-match signals as
specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H’FF at a reset and in the standby modes.
Compare-match is not detected during the T
item (3) in section 8.6, Application Notes.
8.2.3 Timer Control Register (TCR) – H’FFC8 (TMR0), H’FFD0 (TMR1)
Bit
Initial value
Read/Write
TCR is an 8-bit readable/writable register that selects the clock source and the time at which the
timer counter is cleared, and enables interrupts.
TCR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to 1.
(TMR0), H’FFD2 and H’FFD3 (TMR1)
CMIEB CMIEA
R/W
R/W
7
1
7
0
R/W
R/W
6
1
6
0
OVIE
R/W
R/W
5
1
5
0
3
state of a write cycle to TCORA or TCORB. See
CCLR1 CCLR0
154
R/W
R/W
4
1
4
0
R/W
R/W
3
1
3
0
CKS2
R/W
R/W
2
1
2
0
CKS1
R/W
R/W
1
1
1
0
CKS0
R/W
R/W
0
1
0
0