DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 98

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2.3
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Rev. 3.00, 03/04, page 56 of 830
Bit
1
0
Bit
7
6
5
Bit Name
KINWUE
RAME
Bit Name
IICX2
IICX1
IICX0
Serial Timer Control Register (STCR)
0
1
0
0
0
Initial Value
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Keyboard Control Register Access Enable
Enables or disables CPU access for input control
registers (KMIMRA, KMIMR6, WUEMR3) of KINn and
WUEn pins, input pull-up MOS control register
(KMPCR6) of the KINn pin, and registers
(TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X,
TCORB_X) of 8-bit timers (TMR_X, TMR_Y),
0: Enables CPU access for registers of TMR_X and
1: Enables CPU access for input control registers of
RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Description
IIC Transfer Rate Select 2, 1 and 0
These bits control the IIC operation. These bits
select a transfer rate in master mode together with
bits CKS2 to CKS0 in the I
(ICMR). For details on the transfer rate, see table
15.3. The IICXn bit controls IIC_n. (n = 0 to 2)
TMR_Y in an area from H'FFFFF0 to H'FFFFF7 and
from H'FFFFFC to H'FFFFFF.
the KINn and WUEn pins and the input pull-up MOS
control register of the KINn pin in an area from
H'FFFFF0 to H'FFFFF7 and from H'FFFFFC to
H'FFFFFF.
2
C bus mode register