DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 564

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.4
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
• LADR3H
• LADR3L
Rev. 3.00, 03/04, page 522 of 830
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name Initial Value Slave Host
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit Name Initial Value Slave Host
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3

Bit 1
TWRE
LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
All 0
All 0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W





Description
Channel 3 Address Bits 15 to 8
The host address of LPC channel 3 is set.
Description
Channel 3 Address Bits 7 to 3
The host address of LPC channel 3 is set.
Reserved
The initial value should not be changed.
Channel 3 Address Bit 1
The host address of LPC channel 3 is set.
Bidirectional data Register Enable
Enables or disables bidirectional data register
operation.
Clear this bit to 0 in KCS mode.
0: TWR operation is disabled
1: TWR operation is enabled
TWR-related address (LADR3) match does not
occur.