DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 353

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.4
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
TCR_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS
is 1. TCR_X can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section 12.3.11, Timer
Connection Register S (TCONRS).
Bit
7
6
5
4
3
2 to 0
Timer Control Register (TCR)
Bit Name Initial Value R/W Description
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2 to
CKS0
0
0
0
0
0
All 0
R/W Timer Overflow Interrupt Enable
R/W Compare-Match Interrupt Enable B
R/W Compare-Match Interrupt Enable A
R/W
R/W
R/W Clock Select 2 to 0
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
Counter Clear 1 and 0
These bits select the method by which the timer
counter is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
STCR. For details, see table 12.2.
Rev. 3.00, 03/04, page 311 of 830