DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 537

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.6
1. In master mode, if an instruction to generate a start condition is immediately followed by an
Note: * An illegal procedure in the I
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 15.11 shows the timing of SCL and SDA outputs in synchronization with the internal
Table 15.11 I
Note:
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions*, after issuing the instruction that generates the start
condition, read the relevant DR registers of I
both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then
issue the instruction that generates the stop condition. Note that SCL may not yet have gone
low when BBSY is cleared to 0.
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
ICDRS)
ICDRR)
*
Usage Notes
6t
cyc
2
C Bus Timing (SCL and SDA Outputs)
when IICXn is 0, 12t
cyc
when IICXn is 1 (n = 0 to 5).
2
C bus specification.
Symbol Output Timing
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
2
C bus output pins, check that SCL and SDA are
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLLO
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
to 512t
– 3t
– (6t
– 1t
– 1t
+ 2t
cyc
cyc
cyc
cyc
cyc
cyc
or 12t
Rev. 3.00, 03/04, page 495 of 830
cyc
*)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
25.30
(reference)
See figure