DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 708

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.5.2
Software protection is set up in any of two ways: by disabling the downloading of on-chip
programs for programming and erasing and by means of a key code.
Table 20.10 Software Protection
20.5.3
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcomputer entering runaway during programming/erasing of the flash memory or
operations that are not according to the established procedures for programming/erasing. Aborting
programming or erasure in such cases prevents damage to the flash memory due to excessive
programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER
bit in the FCCS register is set to 1 and the error-protection state is entered, and this aborts the
programming or erasure.
The FLER bit is set in the following conditions:
1. When an interrupt such as NMI occurs during programming/erasing.
2. When the flash memory is read during programming/erasing (including a vector read or an
3. When a SLEEP instruction (including software-standby mode) is executed during
4. When a bus master other than the CPU, such as the DTC, gets bus mastership during
Rev. 3.00, 03/04, page 666 of 830
Item
Protection by the
SCO bit
Protection by the
FKEY register
instruction fetch).
programming/erasing.
programming/erasing.
Software Protection
Error Protection
Description
The program/erase-protected state is
entered by clearing the SCO bit in
FCCS which disables the downloading
of the programming/erasing programs.
Downloading and
programming/erasing are disabled
unless the required key code is written
in FKEY. Different key codes are used
for downloading and for
programming/erasing.
Download
Function to be Protected
Program/Erase

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