DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 567

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Notes on determining address match
The IDR3/ODR3/STR3 addresses depend on mode.
Note:
LPC3
E
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SELS
TR3
*
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
*
*
Don't care
KCSE
NBL
*
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
TWRE
*
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
SMIC
ENBL
*
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
*
BTEN
BL
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
Accessible Mode
Channel 3 access
disabled
Normal mode
BT mode
SMIC mode
SMIC/BT mode
TWR mode
TWR/BT mode
TWR/SMIC mode LADR3+2/+3
TWR/SMIC/BT
mode
KCS mode
KCS/BT mode
KCS/SMIC mode LADR3+2/+3
KCS/SMIC/BT
mode
Normal mode
BT mode
SMIC mode
SMIC/BT mode
TWR mode
TWR/BT mode
TWR/SMIC mode LADR3+2/+3
TWR/SMIC/BT
mode
KCS mode
KCS/BT mode
KCS/SMIC mode LADR3+2/+3
KCS/SMIC/BT
mode
Setting prohibited Setting prohibited
IDR3/ODR3/STR3
Host Addresses
Access disabled
LADR3+0/+4
Access disabled
Access disabled
Access disabled
LADR3+0/+4
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
LADR3+0/+4
Access disabled
Access disabled
Access disabled
LADR3+0/+4
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
LADR3+2/+3
Rev. 3.00, 03/04, page 525 of 830
STR3:TWR
Related Bit
Access disabled
TWR flag bit
Access disabled
Access disabled
Access disabled
TWR flag bit
TWR flag bit
TWR flag bit
TWR flag bit
TWR flag bit
TWR flag bit
TWR flag bit
TWR flag bit
User definition bit
Access disabled
Access disabled
Access disabled
TWR flag bit
TWR flag bit
TWR flag bit
TWR flag bit
User definition bit
User definition bit
User definition bit
User definition bit
Setting prohibited