DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 561

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
4
3
2
Bit Name Initial Value Slave Host Description
ABRT
IBFIE3
IBFIE2
0
0
0
R/W
R/W
R/(W)* 
R/W
LPC Abort Interrupt Flag
Interrupt flag that generates an ERRI interrupt when
a forced termination (abort) of an LPC transfer cycle
occurs.
0: [Clearing conditions]
1: [Setting condition]
IBFI3 Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRE in LADR3 = 0]
IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register IDR2 receive completed
1: Input data register IDR2 receive completed
[When TWRE in LADR3 = 1]
completed interrupt requests and SMIC mode and
BT mode interrupt requests are disabled
Input data register IDR3 receive completed
interrupt request and SMIC mode and BT mode
interrupt requests are enabled
Input data register IDR3 and TWR receive
completed interrupt requests and SMIC mode and
BT mode interrupt requests are enabled
interrupt requests disabled
interrupt requests enabled
Writing 0 after reading ABRT = 1
LPC hardware reset
LPC software reset
LPC hardware shutdown
LPC software shutdown
LFRAME pin falling edge detection during LPC
transfer cycle
Rev. 3.00, 03/04, page 519 of 830

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