DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 403

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.6
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, see section
14.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card
interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit
7
6
5
4
3
2
Bit Name
TIE
RIE
TE
RE
MPIE
TEIE
Serial Control Register (SCR)
Initial Value
0
0
0
0
0
0
R/W Description
R/W Transmit Interrupt Enable
R/W Receive Interrupt Enable
R/W Transmit Enable
R/W Receive Enable
R/W Multiprocessor Interrupt Enable (enabled only when
R/W Transmit End Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
When this bit is set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
disabled. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, see
section 14.5, Multiprocessor Communication
Function.
When this bit is set to 1, a TEI interrupt request is
enabled.
Rev. 3.00, 03/04, page 361 of 830