DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 524

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Continuous Receive Operation:
Figure 15.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Rev. 3.00, 03/04, page 482 of 830
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
Read AASX, AAS and ADZ in ICSR
No
No
and TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Set ACKB = 1 in ICSR
Slave receive mode
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read TRS in ICCR
Wait for one frame
and ADZ = 1?
Set MST = 0
(n-2)th-byte
ICDRF = 1?
ESTP = 1 or
ICDRF = 1?
ICDRF = 1?
Read ICDR
Read ICDR
STOP = 1?
Read ICDR
reception?
IRIC = 1?
TRS = 1?
IRIC = 1?
AAS = 1
End
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
No
No
Yes
* n: Address + total number of bytes received
Slave transmit mode
[3] to [7] Wait for one byte to be received (slave address + R/W)
[11] Wait for one byte to be received
[1] Select slave receive mode.
General call address processing
[9] Wait for ACKB setting and set acknowledge data
[10] Read the receive data. The first read is a dummy read.
[12] Detect stop condition
[2] Read the receive data remaining unread.
[8] Clear IRIC
[13] Clear IRIC
[14] Read the last receive data
[15] Clear IRIC
(after the rise of the 9th clock of (n-1)th byte data)
for the last reception
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the rise of the 9th clock)
* Description omitted