DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 609

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4
16.4.1
The LPC interface is activated by setting at least one of bits LPC3E to LPC1E (bits 7 to 5) in
HICR0 to 1. When the LPC interface is activated, the related I/O ports (PE7 to PE0, PD5, and
PD4) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E,
PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports PD3 to PD0) to the LPC
interface's input/output pins.
Use the following procedure to activate the LPC interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
2. Set the I/O addresses of the channels to be used (LADR1 to LADR3) and whether or not the
3. Set the enable bit (LPC3E to LPC1E) for the channel to be used.
4. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be
5. Set the selection bits for other functions (SDWNE, IEDIR).
6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, and OBF). Read IDR or
7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary.
16.4.2
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus mastership memory read, bus mastership memory write, bus mastership I/O
read, and bus mastership I/O write. Of these, the chip's LPC supports only I/O read and I/O write
cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle. However, the LPC in this LSI
always returns a value of B'0000 if the BT interface is not used.
the LPC module is initialized internally.
bidirectional registers, KCS interface, SMIC interface, and BT interface are to be used.
used.
TWR15 to clear IBF.
Operation
LPC Interface Activation
LPC I/O Cycles
Rev. 3.00, 03/04, page 567 of 830