DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 185

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) In Address-Data Multiplex Extended Mode
(a) Program Wait Mode: Program wait mode includes address wait and data wait.
256-kbyte extended area and IOS extended area:
Zero or one state of address wait T
data wait T
CP extended area:
Zero or one state of address wait T
data wait T
(b) Pin Wait Mode: When accessing the external address space, a specified number of wait states
T
is specified by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP
extended area). If the WAIT pin is low at the falling edge of φ in the last T
another T
high.
Pin wait mode is useful when inserting four or more T
T
(c) Pin Auto-Wait Mode: A specified number of wait states T
and T
of φ in the last T
WC0 bits (the WC21 and WC20 bits for the CP extended area). Even if the WAIT pin is held low,
T
Pin auto-wait mode enables the low-speed memory interface only by inputting the chip select
signal to the WAIT pin.
Figure 6.26 shows an example of wait state insertion timing in pin wait mode.
DSW
DOW
DOW
can be inserted between the T
states to be inserted for each external device.
states are inserted only up to the specified number of states.
5
state when accessing the external address space if the WAIT pin is low at the falling edge
DOW
DSW
DSW
state is inserted. If the WAIT pin is held low, T
is inserted between T
is inserted between T
4
state. The number of wait states T
AW
AW
4
4
4
state and T
and T
and T
is inserted between T
is inserted between T
5
5
states.
states.
5
state of data state. The number of wait states T
DOW
DOW
is specified by the settings of the WC1 and
states, or when changing the number of
1
1
and T
and T
DOW
DOW
states are inserted until it goes
Rev. 3.00, 03/04, page 143 of 830
2
2
are inserted between the T
states. Zero to three states of
states. Zero to three states of
4
, T
DSW
, or T
DOW
state,
4
state
DSW

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