DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 459

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8
IrDA operation can be used with SCI_1. Figure 14.36 shows an IrDA block diagram.
If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 signals for SCI_1
are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function
as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves
infrared data communication based on the system defined by the IrDA standard version 1.0.
In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate
of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not
incorporate the capability of automatic modification of the transfer rate; the transfer rate must be
modified through programming.
Transmission: During transmission, the output signals from the SCI (UART frames) are
converted to IR frames using the IrDA interface (see figure 14.37).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
SCICR.
The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 20
MHz, a high-level pulse width of at least 1.41 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
IrDA Operation
TxD1/IrTxD
RxD1/IrRxD
Figure 14.36 IrDA Block Diagram
IrDA
Pulse decoder
SCICR
Pulse encoder
TxD1
RxD1
Rev. 3.00, 03/04, page 417 of 830
SCI_1