DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 315

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 10.5.
Table 10.4 lists the locations of the additional pulses.
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 10.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the
location of base pulse No. 63 according to table 10.4. Thus, an additional pulse of 1/256 × (T) is to
be added to the base pulse.
DA13 DA12 DA11 DA10 DA9
Figure 10.4 Output Waveform (OS = 1, DADR corresponds to T
t
t
t
H1
f1
H1
t
Figure 10.5 D/A Data Register Configuration when CFS = 1
Duty cycle of base pulse
t
t
H1
f1
H1
= t
+ t
= t
+ t
t
f1
t
f2
f1
H2
f2
H2
= t
= t
+ t
+ t
f3
f3
H3
= ··· = t
H3
= ··· = t
+ ··· + t
+ ··· + t
t
f255
H2
t
f63
H2
a. CFS = 0 [base cycle = resolution (T) × 64]
b. CFS = 1 [base cycle = resolution (T) × 256]
H255
DA8
H63
= t
= t
t
f2
t
f2
f256
f64
+ t
+ t
= T× 256
H64
H256
= T× 64
DA7
= T
= T
1 conversion cycle
1 conversion cycle
H
H
DA6
t
H3
t
H3
DA5
Location of additional pulses
DA4
t
H255
t
H63
t
DA3
f255
t
f63
Rev. 3.00, 03/04, page 273 of 830
DA2
t
H256
t
DA1
H64
t
f256
t
f64
DA0
H
)
CFS
1
1