DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 463

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.9.2
Table 14.15 shows the interrupt sources in smart card interface mode. A TEI interrupt request
cannot be used in this mode.
Table 14.15 SCI Interrupt Sources
Data transmission/reception using the DTC is also possible in smart card interface mode, similar
to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously
set to 1, thus generating a TXI interrupt request. This activates the DTC by a TXI interrupt request
thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC
activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer
by the DTC. If an error occurs, the SCI automatically re-transmits the same data. During re-
transmission, the TEND flag remains as 0, thus not activating the DTC. Therefore, the SCI and
DTC automatically transmit the specified number of bytes, including re-transmission in the case of
error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not
automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1
to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC, be sure to set and enable the DTC prior to
making SCI settings. For DTC settings, see section 7, Data Transfer Controller (DTC).
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This
activates the DTC by an RXI interrupt request thus allowing transfer of receive data if the RXI
interrupt request is specified as a source of DTC activation beforehand. The RDRF flag is
automatically cleared to 0 at data transfer by the DTC. If an error occurs, the RDRF flag is not set
but the error flag is set. Therefore, the DTC is not activated and an ERI interrupt request is issued
to the CPU instead; the error flag must be cleared.
Channel Name
0
1
2
Interrupts in Smart Card Interface Mode
ERI0
RXI0
TXI0
ERI1
RXI1
TXI1
ERI2
RXI2
TXI2
Interrupt Source
Receive error, error
signal detection
Receive data full
Transmit data empty
Receive error, error
signal detection
Receive data full
Transmit data empty
Receive error, error
signal detection
Receive data full
Transmit data empty
Interrupt Flag
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
TEND
Rev. 3.00, 03/04, page 421 of 830
DTC Activation
Not possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Possible
Possible
Priority
High
Low