DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 548

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note: Above restrictions can be released by setting the bits FNC1 and FNC2 in ICXR to B'11.
Rev. 3.00, 03/04, page 506 of 830
Though it is prohibited in the normal I
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode.
When the MST bit is set to 1 during data transmission or reception in slave mode, the
arbitration decision circuit is enabled and arbitration is lost if conditions are satisfied. In this
case, the transmit/receive data which is not an address may be erroneously recognized as an
address.
In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may
occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order
below.
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
(Master transmit mode)
(Master transmit mode)
(Slave receive mode)
I2C bus interface
I2C bus interface
the MST bit.
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Other device
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
2
C protocol, the same problem may occur when the MST
A
A
A
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as an
• When the receive data matches to
receive mode
address
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device.
SLA
DATA2
DATA1
R/W
Transmit data does not match
A
A
DATA3
DATA4
Data contention
A
A