DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 462

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.9
14.9.1
Table 14.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data
transfer by the DTC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 14.14 SCI Interrupt Sources
Rev. 3.00, 03/04, page 420 of 830
Channel
0
1
2
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Name
ERI0
RXI0
TXI0
TEI0
ERI1
RXI1
TXI1
TEI1
ERI2
RXI2
TXI2
TEI2
Interrupt Source
Receive error
Receive data full
Transmit data empty
Transmit end
Receive error
Receive data full
Transmit data empty
Transmit end
Receive error
Receive data full
Transmit data empty
Transmit end
Interrupt Flag
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
DTC Activation
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Priority
High
Low

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