DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 275

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
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Quantity:
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Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.11.3
PBPIN indicates the pin states.
Note: The initial value of these pins is determined in accordance with the state of pins PB7 to
8.11.4
Port B is a multi-function port that can function as an event counter input pin. The relationship
between the operating mode setup and pin functions is described below.
When this pin is used as the EVENT input pin according to bits ECSB3 to ECSB0 in ECCR of the
data transfer controller settings, clear the PBnDDR bit to 0.
• PB7/EVENT15
• PB6/EVENT14
Bit
7
6
5
4
3
2
1
0
PB7DDR
Event counter
Pin function
PB6DDR
Event counter
Pin function
PB0.
Bit Name
PB7PIN
PB6PIN
PB5PIN
PB4PIN
PB3PIN
PB2PIN
PB1PIN
PB0PIN
Port B Input Data Register (PBPIN)
Pin Functions
*1
*1
Initial Value
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
PB7 input pin
PB6 input pin
Disable
Disable
R/W
R
R
R
R
R
R
R
R
0
0
EVENT15 input pin
EVENT14 input pin
Description
Pin states can be read by performing a read cycle on
this register.
This register is assigned to the same address as that
of P8DDR. When this register is written to, data is
written to P8DDR and the port 8 setting is then
changed.
Enable
Enable
Rev. 3.00, 03/04, page 233 of 830
(n = 7 to 0 )
PB7 output pin
PB6 output pin
1
1

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