DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 28

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 103
Figure 6.2 IOS Signal Output Timing ........................................................................................ 123
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space).............................. 124
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 125
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 127
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 128
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)........................... 129
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)............................ 130
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 131
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)......................... 132
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) .......................... 133
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 134
Figure 6.13 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 135
Figure 6.14 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 135
Figure 6.15 Bus Timing for 8-Bit, 3-State Access Space ........................................................... 136
Figure 6.16 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) ................... 137
Figure 6.17 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access) ................... 137
Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) .................... 138
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access) .................... 138
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)........................... 139
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)........................... 139
Figure 6.22 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access) ................... 140
Figure 6.23 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access) .................... 140
Figure 6.24 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)........................... 141
Figure 6.25 Example of Wait State Insertion Timing (Pin Wait Mode) ..................................... 142
Figure 6.26 Example of Wait State Insertion Timing................................................................. 144
Figure 6.27 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1).................... 145
Figure 6.28 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0).................... 146
Figure 6.29 Examples of Idle Cycle Operation .......................................................................... 147
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC ............................................................................................. 150
Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 161
Figure 7.3 DTC Register Information Location in Address Space............................................. 162
Figure 7.4 DTC Operation Flowchart......................................................................................... 165
Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 166
Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 167
Figure 7.7 Memory Mapping in Block Transfer Mode .............................................................. 168
Figure 7.8 Chain Transfer Operation.......................................................................................... 169
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 170
Figure 7.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ...................................... 171
Rev. 3.00, 03/04, page xxvi of xl