DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 456

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.7.7
Data reception in smart card interface mode is identical to that in normal serial communication
interface mode. Figure 14.32 shows the data re-transfer operation during reception.
1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI
2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1.
3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined
Figure 14.33 shows a sample flowchart for reception. All the processing steps are automatically
performed using an RXI interrupt request to activate the DTC. In reception, setting the RIE bit to 1
allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates
DTC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is
specified as a source of DTC activate beforehand. The RDRF flag is automatically cleared to 0 at
data transfer by DTC. If an error occurs during reception, i.e., either the ORER or PER flag is set
to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be
cleared. If an error occurs, DTC is not activated and receive data is skipped, therefore, the number
of bytes of receive data specified in DTC are transferred. Even if a parity error occurs and PER is
set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read.
Note: For operations in block transfer mode, see section 14.4, Operation in Asynchronous Mode.
Rev. 3.00, 03/04, page 414 of 830
interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the
next parity bit is sampled.
to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt
request is generated if the RIE bit in SCR is set.
RDRF
PER
Serial Data Reception (Except in Block Transfer Mode)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 14.32 Data Re-transfer Operation in SCI Reception Mode
n th transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransfer frame
(DE)
[3]
[3]
Ds D0 D1 D2 D3 D4
transfer frame
(n + 1) th