DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 431

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4.7
Figure 14.11 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Figure 14.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
RDRF
FER
Serial Data Reception (Asynchronous Mode)
1
Start
bit
0
D0
D1
1 frame
Data
D7
RXI interrupt
request
generated
Parity
bit
0/1
One Stop Bit)
Stop
bit
1
Start
bit
0
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
D0
D1
Data
Rev. 3.00, 03/04, page 389 of 830
D7
Parity
bit
0/1
ERI interrupt request
generated by framing
error
Stop
bit
0
Idle state
(mark state)
1