DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 544

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9. Note on when I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
10. Note on IRIC flag clear when the wait function is used
Rev. 3.00, 03/04, page 502 of 830
In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because
of a large bus load capacity or where a slave device in which a wait can be inserted by driving
the SCL pin low is used, the stop condition instruction should be issued after reading SCL after
the rise of the 9th clock pulse and determining that it is low.
When the wait function is used in I
rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be
inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining
that the SCL is low.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
ICXR.
SDA
SDA
SCL
IRIC
SCL
IRIC
Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1
2
C bus interface stop condition instruction is issued
Figure 15.31 Stop Condition Issuance Timing
SCL = low detected
VIH
VIH
9th clock
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination
[1] SCL = low determination
Secures a high period
Secures a high period
2
C bus interface master mode and in a situation where the
[2] IRIC clear
[2] Stop condition instruction issuance
Stop condition generation