DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 401

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
1
0
Bit
7
6
5
4
Bit Name
Bit Name
GM
BLK
PE
O/E
CKS1
CKS0
Initial Value
0
0
Initial Value
0
0
0
0
R/W Description
R/W
R/W
R/W Description
R/W GSM Mode
R/W Setting this bit to 1 allows block transfer mode
R/W Parity Enable (valid only in asynchronous mode)
R/W Parity Mode (valid only when the PE bit is 1 in
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 14.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 14.3.9, Bit Rate Register
(BRR)).
Setting this bit to 1 allows GSM mode operation. In
GSM mode, the TEND set timing is put forward to
11.0 etu* from the start and the clock output control
function is appended. For details, see section 14.7.8,
Clock Output Control.
operation. For details, see section 14.7.3, Block
Transfer Mode.
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. Set this bit to 1 in smart card
interface mode.
asynchronous mode)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card
interface mode, see section 14.7.2, Data Format
(Except in Block Transfer Mode).
Rev. 3.00, 03/04, page 359 of 830

Related parts for DF2166VT33WV