DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 633

MCU 16BIT FLASH 3V 512K 144-TQFP

DF2166VT33WV

Manufacturer Part Number
DF2166VT33WV
Description
MCU 16BIT FLASH 3V 512K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2166VT33WV

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
106
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2166VT33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.3
The D/A converter has the following registers.
• D/A data register 0 (DADR0)
• D/A data register 1 (DADR1)
• D/A control register (DACR)
17.3.1
DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion.
When analog output is permitted, D/A data register contents are converted and output to analog
output pins.
17.3.2
DACR controls D/A converter operation.
Bit
7
6
5
4 to 0 
Bit Name Initial Value
DAOE1
DAOE0
DAE
Register Descriptions
D/A Data Registers 0 and 1 (DADR0, DADR1)
D/A Control Register (DACR)
0
0
0
All 1
R/W
R/W
R/W
R
R/W
Description
D/A Output Enable 1
Controls D/A conversion and analog output.
0: Analog output DA1 is disabled
1: D/A conversion for channel 1 and analog output DA1
D/A Output Enable 0
Controls D/A conversion and analog output.
0: Analog output DA0 is disabled
1: D/A conversion for channel 0 and analog output DA0
D/A Enable
Controls D/A conversion in conjunction with the DAOE0
and DAOE1 bits. When the DAE bit is cleared to 0, D/A
conversion for channels 0 and 1 are controlled
individually. When the DAE bit is set to 1, D/A conversion
for channels 0 and 1 are controlled as one. Conversion
result output is controlled by the DAOE0 and DAOE1
bits. For details, see table 17.2 below.
Reserved
The initial value should not be changed.
are enabled
are enabled
Rev. 3.00, 03/04, page 591 of 830

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