DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 270

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.10.4
The relationship between the operating mode, register setting values, and pin functions are as
follows.
Normal Extended Mode: Port A functions as address output, keyboard input, external control
input of SCI_0 and SCI_2, and also as an I/O port, and input or output can be specified in bit units.
• PA7/KIN15/EVENT7/A23, PA6/KIN14/EVENT6/A22, PA5/KIN13/EVENT5/A21,
[Legend]
n = 7 to 2
m = 15 to 10
l = 23 to 18
• PA1/KIN9/EVENT1/A17/SSE2I
Rev. 3.00, 03/04, page 228 of 830
PAnDDR
Address 18
Pin function
Address 18 and 13 in the following table are expressed by the following logical expressions:
PA4/KIN12/EVENT4/A20, PA3/KIN11/EVENT3/A19, PA2/KIN10/EVENT2/A18
The function of port A pins is switched according to the combination of address 18 setting and
the PAnDDR bit. When the KMIM bit in KMIMRA of the interrupt controller is cleared to 0,
this pin can be used as the KIN input pin. To use this pin as the KIN input pin, clear the
PAnDDR bit to 0. When this pin is used as EVENT input pin according to bits ECSB3 to
ECSB0 in ECCR of the data transfer controller settings, clear the PAnDDR bit to 0. Though
this pin has been set to the EVENT input pin, to use as the PAn or A1 output pin, set the
PAnDDR bit to 1.
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, address 13 setting, and
the PA1DDR bit.
When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0.
When this pin is used as EVENT1 input pin according to bits ECSB3 to ECSB0 in ECCR of
the data transfer controller settings, clear the PA1DDR bit to 0. Though this pin has been set to
the EVENT1 input pin, to use as the PA1 or A17 output pin, set the PA1DDR bit to 1.
Pin Functions
Address 18 = 1:ADFULLE
Address 13 = 1:ADFULLE
EVENTn input pin
KINm input pin
PAn input pins
0
1
•
CS256E
PAn output pin
•
(CPCSE  IOSE)
1
1
Al output pin
1
0