DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 489

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
5
4
3
Bit Name
MST
TRS
ACKE
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
[MST clearing conditions]
(1) When 0 is written by software
(2) When lost in bus contention in I
[MST setting conditions]
(1) When 1 is written by software (for MST clearing
(2) When 1 is written in MST after reading MST = 0 (for
[TRS clearing conditions]
(1) When 0 is written by software (except for TRS setting
(2) When 0 is written in TRS after reading TRS = 1 (for
(3) When lost in bus contention in I
[TRS setting conditions]
(1) When 1 is written by software (except for TRS clearing
(2) When 1 is written in TRS after reading TRS = 0 (for
(3) When 1 is received as the R/W bit after the first frame
Acknowledge Bit Decision Selection
0: The value of the acknowledge bit is ignored, and
1: If the acknowledge bit is 1, continuous transfer is
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.
mode
condition 1)
MST clearing condition 2)
condition 3)
TRS setting condition 3)
mode
condition 3)
TRS clearing condition 3)
address matching in I
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
halted.
2
Rev. 3.00, 03/04, page 447 of 830
C bus format slave mode
2
2
C bus format master
C bus format master