DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 484

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• I
• Clocked synchronous serial format: non-addressing format without acknowledge bit, for
15.3.4
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Rev. 3.00, 03/04, page 442 of 830
Bit
7
6
5
4
3
master mode only
2
C bus format: addressing format with acknowledge bit
Bit Name
CKS2
CKS1
CKS0
MLS
WAIT
I
2
C Bus Mode Register (ICMR)
Initial
Value
0
All 0
0
R/W Description
R/W MSB-First/LSB-First Select
R/W Wait Insertion Bit
R/W Transfer Clock Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
This bit is valid only in master mode with the I
format.
0: Data and the acknowledge bit are transferred
1: After the fall of the clock for the final data bit (8th clock),
For details, refer to section 15.4.7, IRC Setting Timing and
SCL Control.
These bits are used only in master mode.
These bits select the required transfer rate, together with
the IICX5 (channel 5), IICX4 (channel 4), and IICX3
(channel 3) bits in IICX3, and the IICX2 (channel 2), IICX1
(channel 1), and IICX0 (channel 0) bits in STCR. Refer to
table 15.3.
consecutively with no wait inserted.
the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is
cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
2
C bus format is used.
2
C bus