DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 612

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Slave clears the TX_DATA_RDY bit in SMICFLG.
Slave reads transfer data in SMICDTR according to
Write control code.
Slave writes the status code to SMICCSR to notify
the processing completion status.
Slave clears the BUSY bit in SMICFLG to indicate
transfer completion.
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Rev. 3.00, 03/04, page 570 of 830
Slave confirms that valid data is written to SMICDTR
by host.
The HDTWI bit in SMICIR0 is set.
Slave reads the control code in SMICCSR.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Slave waits for the BUSY bit in SMICFLG is set.
Bit that indicates slave is ready for write transfer.
Issues when slave is ready for the next write transfer.
Slave
Figure 16.4 SMIC Write Transfer Flow
A
A
Abnormal
TX_DATA_RDY = 1
TX_DATA_RDY = 0
Write transfer data
Read transfer data
Wait for BUSY = 0
Write control code
Read control code
Write status code
Read status code
Generate slave
Generate slave
Generate slave
Generate slave
Generate host
BUSY = 1
BUSY = 0
Wait for
interrupt
interrupt
interrupt
interrupt
interrupt
Normal
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Host confirms the TX_DATA_RDY bit in SMICFLG.
The confirmation is unnecessary when Write Start control is issued.
Host writes the Write control code in SMICCSR.
Host writes transfer data in SMICDTR.
Host sets the BUSY bit in SMICFLG.
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
Host