DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 272

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[Legend]
n = 7 to 2
m = 15 to 10
• PA1/KIN9/EVENT1/SSE2I
• PA0/KIN8/EVENT0/SSE0I
Rev. 3.00, 03/04, page 230 of 830
PAnDDR
Pin function
SSE
C/A
CKE1
PA1DDR
Pin function
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, and the PA1DDR bit.
When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0.
When this pin is used as the EVENT1 input pin according to bits ECSB3 to ECSB0 in ECCR
of the data transfer controller settings, clear the PA1DDR bit to 0. Though this pin has been set
to the EVENT1 input pin, to use as the PA1 output pin, set the PA1DDR bit to1.
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, and the PA0DDR bit.
When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN8 input pin. To use this pin as the KIN8 input pin, clear the PA0DDR bit to 0.
When this pin is used as the EVENT0 input pin according to bits ECSB3 to ECSB0 in ECCR
of the data transfer controller settings, clear the PA0DDR bit to 0. Though this pin has been set
to the EVENT0 input pin, to use as the PA0 output pin, set the PA0DDR bit to1.
/EVENT1 input pin
KINm input pin/EVENTn input pins
KIN9 input pin
PA1 input pin
0
PAn input pins
0


0
PA1 output pin
1
PAn output pins
SSE2I input pin
1

1
1
1