AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 967

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

45.3.1.13
45.3.2
45.4
45.4.1
6249H–ATARM–27-Jul-09
Examples of Drawing Functions
Video RAM
Line Draw
Procedure to Switch from Command Queue Drawing to Direct Drawing
The Video RAM type and the address generated to access it are mainly based on data bus type
(8, 16 or 32 bits), on number of bits per pixel and the virtual memory size required by the system.
The TDGC supports SRAM, PSRAM and SDRAM memory chips of 8-bit, 16-bit or 32-bit data
buses. Memory chips can either be external memory (connected to EBI) or internal memory. The
most significant 12 bits of the 32-bit video memory address can be programmed with the
required offset.
The TDGC sees the video memory as a maximum virtual page of 2048(column-x) x 2048(rows-
y) pixels with a pixel resolution up to 24 bpp. Hence, the maximum video memory that TDGC
can see is 12MBytes = 2048 * 2048 * 24/8.
The row size of the virtual memory can be programmed to be 256, 512, 1024 or 2048 pixels.
Since the minimum row size selection is 256 pixels and the next size up is 512 pixels, some
chips that are tailored for 240(column size) x 320(row size) at 8 bpp LCDs have only 80 Kbytes
of internal RAM and thus do not fit in the resolution scheme defined above. In order to make the
TDGC compliant with this kind of use, a special option was added to make 320 pixel wide row at
8 bpp selection possible. However, this slows down the drawing process. For instance, when a
line draw command is issued, the TDGC calculates the row offset based on the start/end pixel
coordinates of the line draw versus a predefined shift in bits for row size selections of 256, 512,
1024 and 2048 (they are all powers of 2 and hence the shift is pre-defined in logic).
There are two suggestions to solve this problem:
However, a pixel resolution of 320(column) x 240(row) at 8 bpp can use the internal memory of
80 Kbytes if necessary, as a row size selection of 256 pixels can be used. There is however no
problem with any ¼ VGA at anything less than 8 bpp.
This function draws a thick (2 pixels wide) solid black line from start point (startx, starty) to end
point (endx, endy). startx, starty, endx, endy should be in pixel units.
• Wait for Command queue buffer empty status (BUFE) in TDGC_GIR with a five second
• Post an event to the graphics task when interrupt is triggered or exit the loop checking for the
• Wait for command queue buffer empty status in TDGC_GIR.
• Wait for line drawing engine bit (LTB bitfield in TDGC_GSR) to clear if a line is being drawn.
• Wait for block transfer engine bit (BTB bitfield in TDGC_GSR) to clear if a block is being
• If a significant amount of drawing using the TDGC is required and 240 x 320 at 8 bpp is not
• If there is a firm requirement for 240 x 320 at 8 bpp, then the special option can be enabled in
timeout or wait for an interrupt event if interrupt is enabled (recommended).
status when command queue buffer is empty (BUFE in TDGC_GIR). Load the next set of
commands (refer to code examples).
transferred.
mandatory, a bigger frame can be used thus taking advantage of the TDGC drawing speed.
the TDGC that makes 240 x 340 at 8 bpp support possible but slow, or the TDGC can be
disabled and software that can be faster is used instead.
AT91SAM9263
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