AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1075

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.3.8
50.3.8.1
6249H–ATARM–27-Jul-09
LCD
LCD Screen Shifting After a Reset
EMACB master interface releases the AHB bus between two transfers.
EMACB has the highest priority.
If we are in a state where EMACB RX and TX FIFOs have requests pending, the following
sequence occurs:
In a case of a slow memory and/or a special operation such as SDRAM refresh or SDRAM bank
opening /closing, there may be TX underrun (latency min 960 ns).
Reduce re-arbitration time between RX and TX EMACB transfer by using internal SRAM (or
another slave with a short access time) for transmit buffers and descriptors.
When a FIFO underflow occurs, a reset of the DMA and FIFO pointers is necessary. Performing
the following sequence:
lead to well reset DMA pointers but not FIFO pointers, the displayed image is shifted.
Apply the following sequence:
1. Receive buffer manager write
2. Receive buffer manager read
3. Transmit data DMA read
4. Receive data DMA write
5. Transmit buffer manager read
6. Transmit buffer manager write
1. EMACB RX FIFO write (burst 4)
2. EMACB release the AHB bus
3. The AHB matrix can grant an another master (ARM I or D for example)
4. AHB matrix re-arbitration (finish at least the current word/halfword/byte)
5. The AHB matrix grants the EMACB
6. The EMACB TX FIFO read (burst 4)
• DMA disable
• Wait for DMABUSY
• DMA reset
• DMA enable
• LCD power off
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9263
1075