AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 295

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

6249H–ATARM–27-Jul-09
Note:
Note:
3. Write the starting destination address in the DMAC_DARx register for channel x.
4. Write the channel configuration information into the DMAC_CFGx register for channel
5. Make sure that all LLI.DMAC_CTLx register locations of the LLI (except the last) are set
6. Make sure that the LLI.DMAC_LLPx register locations of all LLIs in memory (except the
7. Make sure that the LLI.DMAC_SARx register location of all LLIs in memory point to the
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register loca-
9. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx
10. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx
11. Clear any pending interrupts on the channel from the previous DMA transfer by writing
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 8 as shown in
13. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked
14. Finally, enable the channel by writing a ‘1’ to the DMAC_ChEnReg.CH_EN bit. The
15. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
16. Source and destination requests single and burst DMAC transactions to transfer the
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
as shown in Row 8 of
the last Linked List item must be set as described in Row 1 of
on page 284
last) are non-zero and point to the next Linked List Item.
start source block address proceeding that LLI fetch.
tions of all LLIs in memory is cleared.
register for channel x.
register for channel x.
to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock,
DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt
Raw Status and Interrupt Status registers confirms that all interrupts have been
cleared.
Table 25-2 on page 277
List item.
transfer is performed. Make sure that bit 0 of the DMAC_DmaCfgReg register is
enabled.
block of data (assuming non-memory peripherals). The DMAC acknowledges at the
The values in the LLI.DMAC_DARx register location of each Linked List Item (LLI) in memory,
although fetched during an LLI fetch, are not used.
The LLI.DMAC_SARx, LLI.DMAC_DARx, LLI.DMAC_LLPx and LLI.DMAC_CTLx registers are
fetched. The LLI.DMAC_DARx register location of the LLI although fetched is not used. The
DMAC_DARx register in the DMAC remains unchanged.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
peripheral, assign handshaking interface to the source and destination peripherals.
This requires programming the SRC_PER and DEST_PER bits, respectively.
shows a Linked List example with two list items.
Table 25-2 on page
277, while the LLI.DMAC_CTLx register of
Table
AT91SAM9263
25-2.
Figure 25-8
295