AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 191

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

22. Static Memory Controller (SMC)
22.1
22.2
Table 22-1.
22.3
Table 22-2.
6249H–ATARM–27-Jul-09
Name
NCS[7:0]
NRD
NWR0/NWE
A0/NBS0
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
A[25:2]
D[31:0]
NWAIT
NWR0
A0
NWR1
A1
NWR3
Overview
I/O Lines Description
Multiplexed Signals
Multiplexed Signals
NWE
NBS0
NBS1
NWR2
NBS3
I/O Line Description
Static Memory Controller (SMC) Multiplexed Signals
Description
Static Memory Controller Chip Select Lines
Read Signal
Write 0/Write Enable Signal
Address Bit 0/Byte 0 Select Signal
Write 1/Byte 1 Select Signal
Address Bit 1/Write 2/Byte 2 Select Signal
Write 3/Byte 3 Select Signal
Address Bus
Data Bus
External Wait Signal
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parameterizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
NBS2
Related Function
Byte-write or byte-select access, see
8-bit or 16-/32-bit data bus, see
Byte-write or byte-select access see
8-/16-bit or 32-bit data bus, see
Byte-write or byte-select access, see
Byte-write or byte-select access see
“Data Bus Width” on page 194
“Data Bus Width” on page
“Byte Write or Byte Select Access” on page 194
“Byte Write or Byte Select Access” on page 194
“Byte Write or Byte Select Access” on page 194
“Byte Write or Byte Select Access” on page 194
194.
AT91SAM9263
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
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