AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 281

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

6249H–ATARM–27-Jul-09
Note:
3. Write the channel configuration information into the DMAC_CFGx register for channel
4. Make sure that the LLI.DMAC_CTLx register locations of all LLI entries in memory
5. Make sure that the LLI.DMAC_LLPx register locations of all LLI entries in memory
6. Make sure that the LLI.DMAC_SARx/LLI.DMAC_DARx register locations of all LLI
7. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register loca-
8. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx
9. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx
10. Clear any pending interrupts on the channel from the previous DMA transfer by writing
11. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 10 as shown in
12. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked
13. Finally, enable the channel by writing a ‘1’ to the DMAC_ChEnReg.CH_EN bit. The
14. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
15. Source and destination request single and burst DMA transactions to transfer the block
16. The DMAC does not wait for the block interrupt to be cleared, but continues fetching the
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
(except the last) are set as shown in Row 10 of
LLI.DMAC_CTLx register of the last Linked List Item must be set as described in Row 1
of
(except the last) are non-zero and point to the base address of the next Linked List
Item.
entries in memory point to the start source/destination block address preceding that LLI
fetch.
tions of all LLI entries in memory are cleared.
register for channel x.
register for channel x.
to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock,
DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt
Raw Status and Interrupt Status registers confirms that all interrupts have been
cleared.
Table 25-2 on page
List item.
transfer is performed.
of data (assuming non-memory peripheral). The DMAC acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
next LLI from the memory location pointed to by current DMAC_LLPx register and auto-
The LLI.DMAC_SARx, LLI. DMAC_DARx, LLI.DMAC_LLPx and LLI.DMAC_CTLx registers are
fetched. The DMAC automatically reprograms the DMAC_SARx, DMAC_DARx, DMAC_LLPx and
DMAC_CTLx channel registers from the DMAC_LLPx(0).
Table
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DEST_PER bits, respectively.
25-2.
Figure 25-7 on page 283
277.
shows a Linked List example with two list items.
Table 25-2 on page
AT91SAM9263
277. The
281