AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1078
AT91SAM9263B-CU
Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9263B-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625
Available stocks
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Manufacturer
Quantity
Price
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Quantity:
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Part Number:
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Manufacturer:
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50.3.11.2
1078
AT91SAM9263
RSTC: Reset during SDRAM Accesses
None
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while
data is ready to be read on the data bus. The SDRAM maintains the data until the clock restarts.
If the User Reset is programmed to assert a general reset, the data maintained by the SDRAM
leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
In the interrupt routine, power down the SDRAM properly and perform Peripheral and Processor
Reset with software in assembler.
Example with libV3.
• NAND Flash boot functionality, if the system boots out of internal ROM.
• NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
1. Avoid User Reset to generate a system reset.
2. Trap the User Reset with an interrupt.
• The main code:
• The C SYS handler:
• The assembler routine:
Problem Fix/Workaround
//user reset interrupt setting
*AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN;
extern void soft_user_reset(void);
void sysc_handler(void){
//check if interrupt comes from RSTC
}
AREA
// Configure AIC controller to handle SSC interrupts
AT91F_AIC_ConfigureIt (
// Enable SYSC interrupt in AIC
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
soft_user_reset();
//never reached
while(1);
if( (*AT91C_RSTC_RSR & AT91C_RSTC_URSTS ) == AT91C_RSTC_URSTS){
}
AT91C_BASE_AIC,
AT91C_ID_SYS,
AT91C_AIC_PRIOR_HIGHEST,
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive
sysc_handler );
TEST, CODE
// System peripheral ID
// AIC base address
// Max priority
6249H–ATARM–27-Jul-09
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