AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 296

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

Figure 25-15. DMA Transfer with Linked List Source Address and Contiguous Destination Address
296
AT91SAM9263
Source Layer
Address of
SAR(2)
SAR(1)
SAR(0)
The DMAC transfer might look like that shown in
nation address is decrementing.
The DMA transfer flow is shown in
17. The DMAC does not wait for the block interrupt to be cleared, but continues and fetches
completion of every transaction (burst and single) in the block and carry out the block
transfer.
the next LLI from the memory location pointed to by current DMAC_LLPx register and
automatically reprograms the DMAC_SARx, DMAC_CTLx and DMAC_LLPx channel
registers. The DMAC_DARx register is left unchanged. The DMA transfer continues
until the DMAC samples the DMAC_CTLx and DMAC_LLPx registers at the end of a
block transfer match that described in Row 1 of
then knows that the previous block transferred was the last block in the DMA transfer.
Source Blocks
Block 1
Block 2
Block 0
Figure 25-16 on page
Destination Blocks
Block 2
Block 1
Block 0
Figure 25-15 on page 296
Table 25-2 on page
297.
DAR(2)
DAR(0)
DAR(1)
Destination Layer
Address of
277. The DMAC
Note that the desti-
6249H–ATARM–27-Jul-09