AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 923

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

6249H–ATARM–27-Jul-09
In order to locate the displayed window within a larger frame buffer, the software must:
The above configuration can be changed frame to frame, so the displayed window can be
moved rapidly. Note that the FRMSIZE field of DMAFRMCFG register must be updated with any
movement of the displaying window. Note also that the software must write bit DMAUPDT in
DMACON register after each configuration for it to be accepted by LCDC.
Note:
• Program the DMABADDR1 (DMABADDR2) register(s) to make them point to the word
• Program the PIXELOFF field of DMA2DCFG register to specify the offset of this first pixel
• Define the width of the complete frame buffer by programming in the field ADDRINC of
• Enable the 2D addressing mode by writing the DMA2DEN bit in DMACON register. If this bit
containing the first pixel of the area of interest.
within the 32-bit memory word that contains it.
DMA2DCFG register the address increment between the last word of a line and the first word
of the next line (in number of 32-bit words).
is not activated, the values in the DMA2DCFG register are not considered and the controller
assumes that the displayed area occupies a continuous portion of the memory.
In 24 bpp packed mode, the DMA base address must point to a word containing a complete pixel
(possible values of PIXELOFF are 0 and 8). This means that the horizontal origin of the displaying
window must be a multiple of 4 pixels or a multiple of 4 pixels minus 1 (x = 4n or x = 4n-1, valid ori-
gins are pixel 0,3,4,7,8,11,12, etc.).
AT91SAM9263
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