AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 304
AT91SAM9263B-CU
Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9263B-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9263B-CU
Manufacturer:
IDT
Quantity:
1 043
Part Number:
AT91SAM9263B-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT91SAM9263B-CU-100
Manufacturer:
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Quantity:
1 000
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25.4.3
Name: DMAC_LLPx
Addresses:0x00800010 [0], 0x00800068 [1]
Access: Read-write
Reset: 0x0
The address offset for each channel is: 0x10+[x * 0x58]
For example, LLP0: 0x010, LLP1: 0x068, etc.
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not
stored because the address is assumed to be aligned to a 32-bit boundary.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enabled.
The LLP register has two functions:
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists.
304
31
23
15
7
AT91SAM9263
Linked List Pointer Register for Channel x
30
22
14
6
1. The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA trans-
2. The DMAC_LLPx register is also used to point to the address where write back of the
fer (single or multi-block).
control and source/destination status information occurs after block completion.
29
21
13
5
LOC
28
20
12
4
LOC
LOC
LOC
27
19
11
3
26
18
10
2
25
17
9
1
0
6249H–ATARM–27-Jul-09
24
16
8
0
0
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