AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1081

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.3.14.6
50.3.14.7
50.3.14.8
50.3.15
50.3.15.1
50.3.15.2
50.3.15.3
6249H–ATARM–27-Jul-09
Serial Synchronous Controller (SSC)
SPI: SPI Software Reset Must Be Written Twice
SPI: Chip Select and Fixed Mode
SPI: Software Reset Must be Written Twice
Transmitter Limitations in Slave Mode
Periodic Transmission Limitations in Master Mode
Unexpected Delay on TD output
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
None.
In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip
Select 0, the output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 reg-
ister, whatever the selected Chip select may be. For example, if CSR0 is configured for a 10-bit
transfer, whereas the CSR1 is configured for an 8-bit transfer, when a transfer is performed in
Fixed mode through the PDC on Chip Select 1, the transfer is considered to be a half-word
transfer.
If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
If a software reset (SWRST in the control register) is performed, the SPI may not work properly
(the clock is enabled before the chip select).
The SPI Control Register field, SWRST (Software Reset) needs to be written twice to be cor-
rectly set.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
None.
When SSC is configured with the following conditions:
An unexpected delay of 2 or 3 system clock cycles is added to TD output.
• TCMR.STTDLY more than 0
• RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge
• RFMR.FSOS = None (input)
• TCMR.START = Receive Start
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9263
1081