AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 22

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

8.1
8.1.1
8.1.1.1
22
Embedded Memories
AT91SAM9263
Internal Memory Mapping
Internal 80 Kbyte Fast SRAM
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High Performance Bus (AHB) for its master and slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
9 are directed to the EBI0 that associates these banks to the external chip selects EBI0_NCS0
to EBI0_NCS5 and EBI1_NCS0 to EBI1_NCS2. The bank 0 is reserved for the addressing of the
internal memories, and a second level of decoding provides 1M bytes of internal memory area.
Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus
(APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each master has its own bus and its own decoder, thus allowing a different memory mapping for
each master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot and one after remap. Refer to
details.
A complete memory map is presented in
Table 8-1
BMS state at reset.
Table 8-1.
The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split
into three areas. Its memory mapping is presented in
0x0000 0000
• 128 Kbyte ROM
• One 80 Kbyte Fast SRAM
• 16 Kbyte Fast SRAM
• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block
anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
– Supports ARM926EJ-S TCM interface at full processor speed
– Allows internal Frame Buffer for up to 1/4 VGA 8 bpp screen
– Single Cycle Access at full matrix speed
summarizes the Internal Memory Mapping, depending on the Remap status and the
Internal Memory Mapping
Address
Table 8-1, “Internal Memory Mapping,” on page 22
REMAP = 0
BMS = 1
ROM
Figure 8-1 on page
Figure 8-1 on page
BMS = 0
EBI0_NCS0
21.
21.
REMAP = 1
SRAM C
6249H–ATARM–27-Jul-09
for