AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 865
AT91SAM9263B-CU
Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9263B-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
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Part Number:
AT91SAM9263B-CU
Manufacturer:
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Part Number:
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Notes:
43.5.2
43.5.2.1
865
1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data).
AT91SAM9263
Handling Transactions with USB V2.0 Device Peripheral
DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer.
Setup Transaction
Figure 43-4. Control Read and Write Sequences
Setup is a special type of host-to-device transaction used during control transfers. Control trans-
fers must be performed using endpoints with no ping-pong attributes. A setup transaction needs
to be handled as soon as possible by the firmware. It is used to transmit requests from the host
to the device. These requests are then handled by the USB device and may require more argu-
ments. The arguments are sent to the device by a Data OUT transaction which follows the setup
transaction. These requests may also return data. The data is carried out to the host by the next
Data IN transaction which follows the setup transaction. A status transaction ends the control
transfer.
When a setup transfer is received by the USB endpoint:
Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read
the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the
setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data
OUT transfer and overwrite the setup packet in the FIFO.
• The USB device automatically acknowledges the setup packet
• RXSETUP is set in the UDP_CSRx register
• An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is
carried out to the microcontroller if interrupts are enabled for this endpoint.
Control Read
Control Write
No Data
Control
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
Status Stage
Status IN TX
Data OUT TX
Data IN TX
Data Stage
Data Stage
Data OUT TX
Data IN TX
6249H–ATARM–27-Jul-09
Status OUT TX
Status Stage
Status IN TX
Status Stage
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