AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 278

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

25.3.4.3
25.3.4.4
25.3.4.5
278
AT91SAM9263
Auto-reloading of Channel Registers
Contiguous Address Between Blocks
Suspension of Transfers Between Blocks
During auto-reloading, the channel registers are reloaded with their initial values at the comple-
tion of each block and the new values used for the new block. Depending on the row number in
Table 25-2 on page
channel registers are reloaded from their initial value at the start of a block transfer.
In this case, the address between successive blocks is selected to be a continuation from the
end of the previous block. Enabling the source or destination address to be contiguous between
b l o c k s i s a f u n c t i o n o f D M A C _ C T L x . L L P _ S _ E N , D M A C _ C F G x . R E L O A D _ S R ,
DMAC_CTLx.LLP_D_EN, and DMAC_CFGx.RELOAD_DS registers (see
277).
Note:
At the end of every block transfer, an end of block interrupt is asserted if:
Note:
For rows 6, 8, and 10 of
transfers. For example, at the end of block N, the DMAC automatically proceeds to block N + 1.
For rows 2, 3, 4, 7, and 9 of
reloaded between block transfers), the DMA transfer automatically stalls after the end of block.
Interrupt is asserted if the end of block interrupt is enabled and unmasked.
The DMAC does not proceed to the next block transfer until a write to the block interrupt clear
register, DMAC_ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.
For rows 2, 3, 4, 7, and 9 of
reloaded between block transfers), the DMA transfer does not stall if either:
Channel suspension between blocks is used to ensure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
T h i s e n s u r e s t h a t t h e I S R h a s c l e a r e d t h e D M A C _ C F G x . R E L O A D _ S R a n d / o r
DMAC_CFGx.RELOAD_DS bits before completion of the final block. The reload bits
DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS should be cleared in the ‘end of
block ISR’ for the next-to-last block transfer.
• interrupts are enabled, DMAC_CTLx.INT_EN = 1
• the channel block interrupt is unmasked, DMAC_MaskBlock[n] = 0, where n is the channel
• interrupts are disabled, DMAC_CTLx.INT_EN = 0, or
• the channel block interrupt is masked, DMAC_MaskBlock[n] = 1, where n is the channel
number.
number.
Both DMAC_SARx and DMAC_DARx updates cannot be selected to be contiguous. If this func-
tionality is required, the size of the Block Transfer (DMAC_CTLx.BLOCK_TS) must be increased.
If this is at the maximum value, use Row 10 of
LLI.DMAC_SARx address of the block descriptor to be equal to the end DMAC_SARx address of
the previous block. Similarly, setup the LLI.DMAC_DARx address of the block descriptor to be
equal to the end DMAC_DARx address of the previous block.
The block complete interrupt is generated at the completion of the block transfer to the destination.
277, some or all of the DMAC_SARx, DMAC_DARx and DMAC_CTLx
Table 25-2 on page
Table 25-2 on page 277
Table 25-2 on page 277
277, the DMA transfer does not stall between block
Table 25-2 on page 277
(DMAC_SARx and/or DMAC_DARx auto-
(DMAC_SARx and/or DMAC_DARx auto-
and setup the
Figure 25-2 on page
6249H–ATARM–27-Jul-09