AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 303
AT91SAM9263B-CU
Manufacturer Part Number
AT91SAM9263B-CU
Description
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9263B-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
2-Wire, EBI, I2S, MCI, SPI, USART
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
Minimum Operating Temperature
- 40 C
Package
324TFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
200 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Controller Family/series
AT91SAM9xxx
No. Of I/o's
160
Ram Memory Size
96KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3735625
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
AT91SAM9263B-CU
Manufacturer:
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Quantity:
1 043
Part Number:
AT91SAM9263B-CU
Manufacturer:
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Part Number:
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25.4.2
Name: DMAC_DARx
Addresses:0x00800008 [0], 0x00800060 [1]
Access: Read-write
Reset: 0x0
The address offset for each channel is: 0x08+[x * 0x58]
For example, DAR0: 0x008, DAR1: 0x060, etc.
• DADD: Destination Address of DMA transfer
The starting AMBA destination address is programmed by software before the DMA channel is enabled or by a LLI update
before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the destination
address of the current AMBA transfer.
Updated after each destination AMBA transfer. The DINC field in the DMAC_CTLx register determines whether the
address increments, decrements or is left unchanged on every destination AMBA transfer throughout the block transfer.
6249H–ATARM–27-Jul-09
31
23
15
7
Channel x Destination Address Register
30
22
14
6
29
21
13
5
28
20
12
4
DADD
DADD
DADD
DADD
27
19
11
3
26
18
10
2
AT91SAM9263
25
17
9
1
24
16
8
0
303
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