AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1066

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.2.14
50.2.14.1
50.2.15
50.2.15.1
50.2.15.2
50.2.15.3
50.2.15.4
1066
AT91SAM9263
Static Memory Controller (SMC)
Serial Peripheral Interface (SPI)
SMC Chip Select Parameters Modification
SPI: PDC Data Loss
SPI: Pulse Generation on SPCK
SPI: Bad PDC Behavior when CSAAT=1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters while fetching the code
from a memory on CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select.
One byte data can be lost when PDC transmits. This occurs when write accesses are performed
on the base address of any peripheral, during the PDC transfer.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
None.
If the SPI2 is programmed with CSAAT = 1, SCBR (baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the
data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a
"1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Problem Fix/Workaround:
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
– Add a timeout for the PDC transfer and check the value of the PDC transmit counter
– Check the data integrity by a checksum.
– Avoid write access on the base address of peripherals during a PDC transfer.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0.
when the timeout elapsed.
6249H–ATARM–27-Jul-09