AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1083

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.3.19
50.3.19.1
50.3.20
50.3.20.1
50.3.20.2
6249H–ATARM–27-Jul-09
UDP
UHP
Bad Data in the First IN Data Stage
Non-ISO IN Transfers
ISO OUT Transfers
The STOP is not generated.
The line shows: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
Insert a delay of one TWI clock period before step 4.
All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length
Packet. The CRC is correct. Thus the HOST may only see that the size of the received data
does not match the requested length. But even if performed again, the control transfer probably
fails.
Control transfers are mainly used at device configuration. After clearing RXSETUP, the software
needs to compute the setup transaction request before writing data into the FIFO if needed. This
time is generally greater than the minimum safe delay required above. If not, a software wait
loop after RXSETUP clear may be added at minimum cost.
Conditions:
Consider the following scenario:
Consequence: When this error occurs, the Host controller tries the same IN token again.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following scenario:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to do two Write transactions (TD status write and
5. Host controller raises the request for the first write transaction. By the time the transac-
6. After completing the first write transaction, the Host controller skips the second write
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
TD retirement write) to the system memory in order to complete the status update.
tion is completed, a frame boundary is crossed.
transaction.
AT91SAM9263
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