AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 56

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

11.4
56
CP15 Coprocessor
AT91SAM9263
Table 11-4.
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the
items in the list below:
To control these features, CP15 provides 16 additional registers. See
Table 11-5.
Mnemonic
EOR
LSL
ASR
MUL
B
BX
LDR
LDRH
LDRB
LDRSH
LDMIA
PUSH
BCC
• ARM9EJ-S
• Caches (ICache, DCache and write buffer)
• TCM
• MMU
• Other system options
Register
0
0
0
1
2
3
4
5
5
6
7
Operation
Logical Exclusive OR
Logical Shift Left
Arithmetic Shift Right
Multiply
Branch and Exchange
Load Word
Load Half Word
Load Byte
Load Signed Halfword
Load Multiple
Push Register to stack
Conditional Branch
Thumb Instruction Mnemonic List (Continued)
CP15 Registers
Branch
Name
ID Code
Cache type
TCM status
Control
Translation Table Base
Domain Access Control
Reserved
Data fault Status
Instruction fault status
Fault Address
Cache Operations
(1)
(1)
(1)
(1)
(1)
Mnemonic
ORR
LSR
ROR
BLX
BL
SWI
STR
STRH
STRB
LDRSB
STMIA
POP
BKPT
Operation
Logical (inclusive) OR
Logical Shift Right
Rotate Right
Branch, Link, and Exchange
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Load Signed Byte
Store Multiple
Pop Register from stack
Breakpoint
Read/Unpredictable
Read/Unpredictable
Read/Unpredictable
Read/write
Read/write
Read/write
None
Read/write
Read/write
Read/write
Read/Write
Read/Write
Table
11-5.
6249H–ATARM–27-Jul-09