AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 311

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

25.4.7
Name: DMAC_CFGxH
Addresses:0x00800044 [0], 0x0080009C [1]
Access: Read-write
Reset: 0x0
• FCMODE: Flow Control Mode
Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller.
0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled.
1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of
data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termi-
nation by the destination. Data pre-fetching is disabled.
• FIFO_MODE: R/W 0x0 FIFO Mode Select
Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced.
0 = Space/data available for single AMBA transfer of the specified transfer width.
1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO
depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
• PROTCTL: Protection Control
bits used to drive the AMBA HPROT[3:1] bus. The AMBA Specification recommends that the default value of HPROT indi-
cates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access.
• HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the
DMAC_CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source
peripheral connected to that interface via the assigned hardware handshaking interface.
For correct DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
• DEST_PER: Destination Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the
DMAC_CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the desti-
nation peripheral connected to that interface via the assigned hardware handshaking interface.
For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
6249H–ATARM–27-Jul-09
of these register bits to the HPROT[3:1] master interface signals. SRC_PER: Source Hardware Handshaking
Interface
SRC_PER
31
23
15
–
–
–
7
Configuration Register for Channel x High
30
22
14
–
–
6
–
29
21
13
–
–
5
–
DEST_PER
28
20
12
–
–
4
PROTCTL
27
19
11
–
–
3
26
18
10
–
–
2
FIFO_MODE
AT91SAM9263
SRC_PER
25
17
–
–
9
1
FCMODE
24
16
–
–
8
0
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