AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1087

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

51. Revision History
6249H–ATARM–27-Jul-09
Revision
6249H
Comments
Erratum “RSTC: Reset during SDRAM Accesses” removed from Rev A
Erratum “SDCLK Clock Active after Reset “removed from Rev B
47.3.2 “Power Sequence“ moved to a
EBI0_NCS3 restriction added to
In
Matrix (MATRIX) User
1st column header of
Section 33. “Two-wire Interface (TWI)” on page 477
Erratum added to rev A as
rev B as
Voltage row added to
Rev A and B MCI errata
Bit values changed in
‘
page 1026
Second paragraph in
Section 47.8.4 “SDRAMC Signals” on page 1044
Table 47-27, ”SDRAMC Clock Signal”, on page 1044
‘Selectable by software...’ removed from
3 Rev B errata added: USART
Section 50.3.15.3 “Unexpected Delay on TD output” on page
on page
Rev A USART errata
All peripheral clocks are deactivated’ added to
Section 20. ”AT91SAM9263 Bus
Section 50.2.13.1 “RSTC: Reset during SDRAM Accesses” on page 1065
1082.
The most recent version appears first in the tables that follow.
Section 50.2.21.4 on page 1071
Section 5.3 “Programmable I/O Lines Power Supplies” on page 13
Table 49-1, ”AT91SAM9263 Ordering Information”, on page 1058
Table 47-8, ”XIN Clock Electrical Characteristics”, on page
Section 28.9.16 “PMC Interrupt Mask Register” on page
Interface”.
”SDIO interrupt does not work with slots other than A”
Section 50.2.13.1 “RSTC: Reset during SDRAM Accesses” on page
Section 50.3.21.6 “Bad value in Number of Errors Register” on page
Matrix”, slave number changed from 7 to 6 in ”Description”, and in
Section 10.4.2 “ETM
Section 47.4 on page 1029
Table 47-2, ”DC Characteristics”, on page
edited, 2 tables inserted.
changed: TWI2_6212E.fm --> TWI_6212C.fm.
Section 47.3.1 “Power Consumption versus Modes” on
edited.
to
Section 50.2.21.6 on page 1072
™
” on page 41
1081, and PWM
Section 50.3.16.1 “Zero Period”
375.
edited.
1031.
1025.
edited.
edited.
duplicated to Rev B. 6475
AT91SAM9263
1065, and to
1085, SSC
”Bus
Change
Request
Ref.
RFO
6053
6055
6066
6081
6083
6165
6169
6311
6343
6395
6396
6402
6466
1087