AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 306

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

• SINC: Source Address Increment
Indicates whether to increment or decrement the source address on every source AMBA transfer. If your device is fetching
data from a source peripheral FIFO with a fixed address, then set this field to “No change”.
00 = Increment
01 = Decrement
1x = No change
• DEST_MSIZE: Destination Burst Transaction Length
Number of data items, each of width DMAC_CTLx.DST_TR_WIDTH, to be written to the destination every time a destina-
tion burst transaction request is made from either the corresponding hardware or software handshaking interface.
• SRC_MSIZE: Source Burst Transaction Length
Number of data items, each of width DMAC_CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst
transaction request is made from either the corresponding hardware or software handshaking interface.
• S_GATH_EN: Source Gather Enable Bit
0 = Gather is disabled.
1 = Gather is enabled.
Gather on the source side is only applicable when the DMAC_CTLx.SINC bit indicates an incrementing or decrementing
address control.
• D_SCAT_EN: Destination Scatter Enable Bit
0 = Scatter is disabled.
1 = Scatter is enabled.
Scatter on the destination side is only applicable when the DMAC_CTLx.DINC bit indicates an incrementing or decrement-
ing address control.
• TT_FC: Transfer Type and Flow Control
The following transfer types are supported.
• Memory to Memory
• Memory to Peripheral
• Peripheral to Memory
Flow Control can be assigned to the DMAC, the source peripheral, or the destination peripheral.
306
TT_FC
000
001
010
011
100
101
110
111
AT91SAM9263
Transfer Type
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Memory to Peripheral
Peripheral to Peripheral
Peripheral
Source Peripheral
Peripheral
Destination Peripheral
Flow Controller
DMAC
DMAC
DMAC
DMAC
6249H–ATARM–27-Jul-09