AT91SAM9263B-CU Atmel, AT91SAM9263B-CU Datasheet - Page 1071

• Manufacturer Part Number: AT91SAM9263B-CU
• Description: IC ARM9 MCU 200 MHZ 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9263B-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: CAN, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: 2-Wire, EBI, I2S, MCI, SPI, USART
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9263-EK
• Minimum Operating Temperature: - 40 C
• Package: 324TFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 200 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 160
• Ram Memory Size: 96KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: AT91SAM9263-EK - KIT EVAL FOR AT91SAM9263AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3735625

50.2.21
50.2.21.1
50.2.21.2
50.2.21.3
50.2.21.4
50.2.21.5
6249H–ATARM–27-Jul-09
USART
SCK1 and SCK2 are Inverted
RXBRK Flag Error in Asynchronous Mode
RTS not Expected Behavior
Two characters sent if CTS rises during emission
TXD signal is floating in Modem and Hardware Handshaking mod
the resume event, then the Host controller terminates sending the resume signal with an EOP to
the device.
Consequence: If the Device does not recognize the resume (<20 ms) event then the Device, it
will remain in the suspend state.
Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL.
SCK1 and SCK2 clocks are inverted on the PIO controller, but the enable of the clocks is
correct.
This makes it impossible to use USART1 and USART2 in Synchronous Mode.
To use USART1 in Synchronous Mode, the user must program USART1 and USART2 with
exactly the same configuration. SCK2 clock will output on PD10.
Note: EBI0_CFCE2 usage on "periph A" is not forbidden because PD9 is SCK1 which is not
used.
When timeguard is 0, RXBRK is not set when the break character is located just after the Stop
Bit. FRAME (Frame Error) is set instead.
Timeguard should be > 0.
None.
If CTS rises to 1 during a character transmit, the Transmit Holding Register is also transmitted if
not empty.
None.
TXD signal should be pulled up in Modem and Hardware Handshaking mode.
TXD is multiplexed with PIO which integrates a pull up resistor. This internal pull-up must be
enabled.
1. Setting the receiver to hardware handshaking mode drops RTS line to low level even if
2. Disabling the receiver during a PDC transfer while RXBUFF flag is '0' has no effect on
Problem Fix/Workaround
Problem Fix/ Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
the receiver is still turned off. USART needs to be completely configured and started
before setting the receiver to hardware handshaking mode.
RTS. The only way to get the RTS line to rise to high level is to reset both PDMA buffers
by writing the value '0' in both counter registers.
AT91SAM9263
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